Accompanying the development of digital technology and the spread of high speed Internet in recent years, there is a demand for higher performance in personal computers, commercial consumer devices that require high capacity digital data processing, and routers and servers for data communication processing for such devices. Accompanying this, increasingly large capacities of band width for inter-chip communication I/O are being promoted, and there is a demand for wired communication technology that enables large capacity communication at low cost. In particular, regarding inter-chip wired communication of 10 gigabits or more, in a communication transmission board, waveform attenuation occurs due to cable skin effect or dielectric loss, and waveform distortion is very large, so that high speed waveform equalization technology is becoming necessary.
Patent Document 1 discloses decision feedback equalizer (DFE) technology in which a decision feedback signal is at full rate (1 bit time) for binary transmission. A configuration is such that, in a case where a received signal is 1, a signal multiplied by a prescribed gain in a DAC from a digital signal determined by a sampler, is fed back to an adder before the sampler, addition or subtraction of a signal waveform of a subsequent bit is performed, and intersymbol interference (ISI) generated subsequently is eliminated. As a result, it is possible to eliminate the ISI generated particularly markedly in a high speed serial link.
[Patent Document 1]
    JP Patent Kokai Publication No. JP2005-020750A